97 lines
6.8 KiB
Plaintext
97 lines
6.8 KiB
Plaintext
// <<< Use Configuration Wizard in Context Menu >>>
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// <h> Debug MCU Configuration
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// <o0.0> DBG_SLEEP
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// <i> Debug Sleep Mode
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// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
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// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
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// <o0.1> DBG_STOP
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// <i> Debug Stop Mode
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// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
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// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
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// <o0.2> DBG_STANDBY
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// <i> Debug Standby Mode
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// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
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// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
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// <o0.8> DBG_IWDG_STOP
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// <i> Debug independent watchdog stopped when core is halted
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// <i> 0: The watchdog counter clock continues even if the core is halted
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// <i> 1: The watchdog counter clock is stopped when the core is halted
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// <o0.9> DBG_WWDG_STOP
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// <i> Debug window watchdog stopped when core is halted
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// <i> 0: The window watchdog counter clock continues even if the core is halted
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// <i> 1: The window watchdog counter clock is stopped when the core is halted
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// <o0.10> DBG_TIM1_STOP
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// <i> Timer 1 counter stopped when core is halted
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// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
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// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
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// <o0.11> DBG_TIM2_STOP
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// <i> Timer 2 counter stopped when core is halted
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// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
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// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
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// <o0.12> DBG_TIM3_STOP
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// <i> Timer 3 counter stopped when core is halted
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// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
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// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
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// <o0.13> DBG_TIM4_STOP
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// <i> Timer 4 counter stopped when core is halted
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// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
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// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
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// <o0.14> DBG_CAN1_STOP
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// <i> Debug CAN1 stopped when Core is halted
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// <i> 0: Same behavior as in normal mode
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// <i> 1: CAN1 receive registers are frozen
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// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
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// <i> I2C1 SMBUS timeout mode stopped when Core is halted
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// <i> 0: Same behavior as in normal mode
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// <i> 1: The SMBUS timeout is frozen
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// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
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// <i> I2C2 SMBUS timeout mode stopped when Core is halted
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// <i> 0: Same behavior as in normal mode
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// <i> 1: The SMBUS timeout is frozen
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// <o0.17> DBG_TIM8_STOP
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// <i> Timer 8 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.18> DBG_TIM5_STOP
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// <i> Timer 5 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.19> DBG_TIM6_STOP
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// <i> Timer 6 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.20> DBG_TIM7_STOP
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// <i> Timer 7 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.21> DBG_CAN2_STOP
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// <i> Debug CAN2 stopped when Core is halted
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// <i> 0: Same behavior as in normal mode
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// <i> 1: CAN2 receive registers are frozen
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// <o0.25> DBG_TIM12_STOP
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// <i> Timer 12 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.26> DBG_TIM13_STOP
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// <i> Timer 13 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.27> DBG_TIM14_STOP
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// <i> Timer 14 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.28> DBG_TIM9_STOP
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// <i> Timer 9 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.29> DBG_TIM10_STOP
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// <i> Timer 10 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.30> DBG_TIM11_STOP
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// <i> Timer 11 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// </h>
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DbgMCU_CR = 0x00000007;
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// <<< end of configuration section >>> |